(1) Field of the Invention
The present invention relates to a synchronism detection and demodulating circuit for reproducing digital data which was divided into sync blocks and recorded in that format.
(2) Description of the Prior Art
There have been digital modulating techniques by which a digital data stream consisting of n-bit words is divided every m words and these are grouped as a unit, each group being added with extra `p` bits, to produce one block of {(n.times.m)+p} bits. As an example, the data stream of 8 bit words is divided every three words and these are and grouped as a unit to form a data group of 24 bits, each group being added with extra one bit, to form one block of 25 bits. This method is called the 24/25 modulating scheme.
FIG. 1 shows the track pattern for digital video tape recorders based on the helical scanning technique. The track pattern is composed of four kinds of areas: ITI region where information such as a data format within the track, the absolute position on the track which the rotary head is scanning, etc., is recorded; AUDIO region where the audio signal is recorded; VIDEO region where the video signal is recorded; and SUBCODE region where extra-functional information is recorded, with gaps provided between the regions.
In this track pattern, three regions, i.e., AUDIO region, VIDEO region and SUBCODE region are modulated based on the 24/25 modulation scheme. In FIGS. 2, (A), (B) and (C) show the sync block structures of AUDIO region, VIDEO region and SUBCODE region, respectively. Here, in AUDIO and VIDEO regions, two blocks (called pre-sync blocks) are provided at the beginning of the region and one sync block and change "(two different" to provided at the of a region end. The pre-sync blocks facilitate the detection of the following blocks and the post-sync block indicates the end of the region.
In FIG. 2, a, b and c designate different groups each having an identical block length and the same data format within the sync block.
FIG. 3(1) and FIG. 3(2) show bit patterns of sync blocks. FIG. 3(1) shows a bit pattern before the 24/25 modulation and FIG. 3(2) a bit pattern after the 24/25 modulation. The ID which indicates the order of blocks and extra information for the data before modulation, ID parity for detecting or correcting an error in ID, and the audio signal, video signal, or extra-functional information (the audio signal, video signal and extra-functional information will be generically called `recording information`, hereinbelow), are subjected to a scrambling process for an MOD2 addition of an M-series random signal in order to enhance the random characteristic of the data. Then, in order to prevent the continuation of identical bits and control the d.c. component of the data, one bit is added to three words, or 24 bits. The aforementioned scrambling process is effected in the circuit shown in FIG. 4, where a signal 401 with the extra bit added and a signal 402 which is generated by delaying the signal 401 after the 24/25 modulation by a span of two clock units, are subjected to the MOD2 addition to complete a pre-coding process.
Whether the extra bit is set at `1` or `0` is determined in accordance with the rule of the modulation for preventing the continuation of identical bits and controlling the d.c. component of the data. For a sync pattern, neither the scrambling process nor the pre-coding process is effected, but in order to prevent the continuation of identical bits and control the d.c. component of the data, one of two kinds of sync patterns of 17 bits, which have inverse allocations of bits `1` and `0`, is selected to be added prior to the ID.
A conventional synchronism detection and demodulating process for the data recorded based on this 24/25 modulation scheme is now described. With reference to the drawings, the operation of a conventional synchronism detection and demodulating circuit will be explained. FIG. 5 is a block diagram showing a conventional synchronism detection and demodulating circuit. A reference numeral 501 indicates a serial-to-parallel converter circuit which converts regenerative data 512 inputted to a serial input into parallel data 514 of 5 bits and outputs the result whilst receiving a regenerative clock 513 and frequency divides it by 5 to output the result as a parallel clock 515. Designated at 502 is a delay circuit which delays parallel data 514 using shift registers based on parallel clock 515 so as to output delayed parallel data 516 and it also outputs tap data 517 from the mid tap of each register.
Sync pattern detecting circuit 503 detects sync patterns from tap data 517 and outputs a sync pattern detection pulse 518 which will become true when a sync pattern is detected while the aftermentioned window 528 is set to be true, and outputs a synchronous phase 519 indicating at which position the beginning of the sync pattern is located in the five bits of parallel data 514.
ID detecting circuit 504 detects the ID and ID parity of tap data 517 when the aftermentioned protective sync pattern detecting pulse 522 has become true, based on synchronous phase 519. Circuit then outputs the detected ID 521 and checks ID errors based on the detected ID and ID parity to output an ID error flag 520 which will become true when the ID contains errors.
Sync block protecting circuit 505 checks whether there is a sync block within parallel data 514, based on sync pattern detection pulse 518, ID 521, ID error flag 520, synchronous phase 519 and window 528 which is outputted from the window circuit 506 which will be explained later. If circuit 505 determines that there is a sync block, it outputs a synchronism establishment flag 527 which becomes true if a sync block has been found. After the flag becomes true, the sync pattern and ID are checked at the predictive position indicated by window 528 and then, if errors occur N times (N is an integer equal to 1 or above) in a row, this flag 527 becomes false. Circuit 505 further outputs a sync block detection pulse 525 which indicates the beginning of the sync block, based on sync pattern detection pulse 518 when sync pattern detection pulse 518 has become true while window 528 is true, or by determining the beginning of the sync block based on window 528 even when the sync pattern detection pulse is false while window 528 is true and if synchronism establishment flag 527 is true. The circuit 505 also outputs a retained synchronous phase 524 which is held by sampling synchronous phase 519 at the moment when sync pattern detection pulse 518 becomes true while window 528 is true and outputs an protection ID 526 by correcting the ID, if it contains any error, based on the continuity of ID.
Window circuit 506 predicts which position the next sync pattern falls based on synchronism establishment flag 527, sync block detection pulse 525, protection ID 526 and retained synchronous phase 524 and outputs the predictive position and window 528 which becomes true only when the synchronism establishment flag stays false.
Barrel shifter 507 and a rate converter circuit 508, based on sync block detection pulse 525 and retained synchronous phase 524, delete extra bits in delayed parallel data 516 and output converted parallel data 529 made up of 8 bits which was converted from delayed parallel data 516 made up of 5 bits. This rate converter circuit 508 has memory capable of storing about 90 bytes (one sync).
Descrambling circuit 509, in order to undo the scrambling process which was performed at recording, carries out a descrambling process by which an MOD2 addition of the identical M-series random signal is performed at the same timing as that at the recording operation, thus outputting descrambled data 530.
Modified ID inserting circuit 510 inserts a protection ID 526 into a position at the beginning of descrambled data 530 to output demodulated data 531.
Serial-to-parallel converter circuit 501 receives serial regenerative data 512, or x(0), x(1), x(2) . . . , in this order, and outputs parallel data 514, or X(0,4), X(5,9), X(10,14) . . . , in this order. Here, X(0,4) represents the data from x(0) to x(4) arranged in parallel. Delay circuit 502 is composed of nine-step shift registers each made up of five bits. The first register is designated at T1, the second one is designated at T2, and in this way, the final register is designated at T9.
Regenerative data 512 is the data which was detected at partial response (1, 0, -1). Since the sync pattern is not pre-coded, the leading two bits within the 17 bits of the sync pattern can not take fixed values because they are affected by the two bits right before the sync pattern. Therefore, sync pattern detecting circuit 503 detects 15 bits from the rear end within 17 bits of the reproduced sync pattern as a sync pattern. From now on, the leading position of a sync pattern of 15 bits is referred to as the beginning of the sync pattern. Since regenerative data 512 inputted in serial is converted into 5 bit parallel data, regardless of the position in the sync pattern, there are five positions at which the beginning of the sync pattern can be located.
An example where X(0,4) is outputted to T9 is now be considered. In this case, sync pattern detecting circuit 503 receives as tap data, T9, T8, T7, each made up of 5 bits and the leading 4 bits of T6, in total, 19 bits (X(0, 18)). ID detecting circuit 504 receives as tap data, T6, T5, T4, T3 and T2, each made up of 5 bits and the leading 4 bits of T1, in total, 29 bits (X(15, 43)).
Sync pattern detecting circuit 503 causes sync pattern detection pulse 518 to be true when the beginning of a sync pattern is detected from the output from T9, and determines synchronous phase 519 that indicates at which bit in T9 the beginning of the sync pattern is located. For example, when the beginning of the sync pattern is at X(0), synchronous phase 519 is set at `000`. When the beginning of the sync pattern is at X(4), synchronous phase 519 is set at `100` in order to indicate that the beginning of the sync pattern is in the final bit in T9.
ID detecting circuit 504 detects the ID within tap data 517 and its ID parity based on sync pattern detection pulse 518 and synchronous phase 519. For example, if synchronous pattern detection pulse 518 is true and at the same time, synchronous phase 519 is `000`, one byte in the front half of the ID (to be referred to as ID0, hereinbelow) is found to be X(15, 22), one byte in the rear half of the ID (to be referred to as ID1, hereinbelow) is to be X(24, 31), and the ID parity (to be referred to as IDP) is to be X(32, 39). If sync pattern detection pulse 518 is true and at the same time synchronous phase 519 is `100`, the ID0 is found to be X(19, 26), the ID1 is to be X(28, 35) and the IDP is to be (36, 43). ID detecting circuit 504 outputs the detected ID 521, and checks errors of the ID based on the ID parity to output ID error flag 520.
When synchronism establishment flag 527 is false, sync block protecting circuit 505 judges that there is a sync block if window 528 and sync pattern detection pulse 518 are true and if ID error flag 520 is false, and it causes sync block detection pulse 525 and synchronism establishment flag to be true and loads synchronous phase 519 to retain it as retained synchronous phase 524. When synchronism establishment flag 527 is true, the flag 527 will be set to be false if the state in which at least any one of the following conditions 1, 2 and 3 is not satisfied has been detected N times in a row.
The conditions to be checked are: in the duration within which window 528 is true,
Condition 1--sync pattern detection pulse 518 is true; PA1 Condition 2--ID error flag 520 is false; and PA1 Condition 3--the ID predicted from the ID 521 which was detected when past ID error flag 520 was false corresponds to the currently detected ID 521. PA1 a first circuit which shapes the serially inputted regenerative data into a parallel form using an irregularly frequency-divided clock signal which is frequency divided by m/((n.times.m)+p); PA1 a second circuit which detects sync patterns from the data in the parallel form from the first circuit whilst deleting redundant part in the parallel data; PA1 a third circuit which detects ID information from the data in the parallel form from in the first circuit whilst deleting redundant part in the parallel data; PA1 a fourth circuit which effects synchronism protection based on the information from the second and third circuits; and PA1 a fifth circuit which rearranges the data in the parallel form from the first circuit, based on the information from the fourth circuit whilst deleting the extra bits and redundant part in the parallel data.
For synchronism protection, in the duration within which synchronism establishment flag 527 is true, if sync pattern detection pulse 518 does not become true while the window is true, the position of sync pattern detection pulse 518 is predicted based on window 528 so that sync block detection pulse 525 is caused to be true to retain the previous value of retained synchronous phase 524. For the purpose of ID protection, even if sync pattern detection pulse 518 remains true or if ID error flag 520 at the predicted position of sync pattern detection pulse 518 is true, the current ID is predicted based on the past ID of the sync block so as to output protection ID 526.
Window circuit 506 predicts the position of the next sync pattern based on sync block detection pulse 525 and protection ID 526 and outputs window 528. Barrel shifter 507 calculates the leading position of the synchronism based on retained synchronous phase, and rearranges the data so as to output the arranged data. Rate converter circuit 508 writes 24 bits other than extra bits in the lined-up data 532 into the memory. The data stored in the memory is read out per 8 bits based on a different clock to output converted parallel data 529. Descrambling circuit 509 performs the MOD2 addition of the converted parallel data 529 to the same M-series random signal at recording, outputting descrambled data 530. The modified ID is inserted into the beginning of descrambled data 530, producing demodulated data 531, which is sent to a code error correcting section 511.
In a modulating scheme in which p bits are added as extra bits to m words, when p is not an integer multiple of m (in the conventional example, m=3, p=1; p is one-third of m), there are some cases where demodulated data which is arranged based on word units cannot be obtained if the synchronism detection and demodulating process are effected with reference to a frequency divided clock which is regularly divided as in the conventional example. Therefore, memory for a rate converter circuit for converting the data width, is needed. If due to some reason the frequency of the clock for performing a synchronism detecting process largely shifts from that of the clock for the code error correcting section, there is a risk that erroneous data might be supplied to the code error correcting section; for example, the data before being written in might be read out. Moreover, if this synchronism detection and demodulating section and the code error correcting section are integrated into one chip as an LSI, two cycles of the clocks of 5 bit cycle and 8 bit cycle are present so that the circuit structure becomes complicated to match the timing between these clocks.